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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 50 mhz, 80 db demodulating logarithmic amplifier with limiter output AD606 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features logarithmic amplifier performance C75 dbm to +5 dbm dynamic range 1.5 nv/ ? hz input noise usable to >50 mhz 37.5 mv/db voltage output on-chip low-pass output filter limiter performance 6 1 db output flatness over 80 db range 6 3 8 phase stability at 10.7 mhz over 80 db range adjustable output amplitude low power +5 v single supply operation 65 mw typical power consumption cmos compatible power-down to 325 m w typ <5 m s enable/disable time applications ultrasound and sonar processing phase-stable limiting amplifier to 100 mhz received signal strength indicator (rssi) wide range signal and power measurement product description the AD606 is a complete, monolithic logarithmic amplifier using a 9-stage successive-detection technique. it provides both logarithmic and limited outputs. the logarithmic output is from a three-pole post-demodulation low-pass filter and p rovides a loadable output voltage of +0.1 v dc to +4 v dc. the logarith- mic scaling is such that the output is +0.5 v for a sinusoidal in- put of C75 dbm and +3.5 v at an input of +5 dbm; over this range the logarithmic linearity is typically within 0.4 db. all scaling parameters are proportional to the supply voltage. the AD606 can operate above and below these limits, with re- duced linearity, to provide as much as 90 db of conversion range. a second low-pass filter automatically nulls the input off- set of the first stage down to the submicrovolt level. adding ex- ternal capacitors to both filters allows operation at input frequencies as low as a few hertz. the AD606s limiter output provides a hard-limited signal out- put as a differential current of 1.2 ma from open-collector outputs. in a typical application, both of these outputs are loaded by 200 w resistors to provide a voltage gain of more than 90 db from the input. transition times are 1.5 ns, and the phase is stable to within 3 at 10.7 mhz for signals from C75 dbm to +5 dbm. the logarithmic amplifier operates from a single +5 v supply and typically consumes 65 mw. it is enabled by a cmos logic level voltage input, with a response time of <5 m s. when dis- abled, the standby power is reduced to <1 mw within 5 m s. the AD606j is specified for the commercial temperature range of 0 c to +70 c and is available in 16-pin plastic dips or soics. consult the factory for other packages and temperature ranges. functional block diagram lmlo opcm vlog bfin ilog comm inlo isum 3 2 1 4 5 6 8 7 14 15 16 13 12 11 9 10 ladj fil1 fil2 vpos prup comm lmhi inhi x2 reference and power up offset-null low-pass filter AD606 high-end detectors final limiter 9.375k w 9.375k w 12 m a/db main signal path 11.15 db/stage 2 m a/db 1.5k w 30k w 250 w 30k w x1 360k w 1.5k w 30pf 30pf two-pole sallen-key filter 2pf 360k w one-pole filter 2pf
AD606Cspecifications (@ t a = +25 8 c and supply = +5 v unless otherwise noted; dbm assumes 50 v ) rev. 0 C2C model AD606j parameter conditions min typ max units signal input log amp f max ac coupled; sinusoidal input 50 mhz limiter f max ac coupled; sinusoidal input 100 mhz dynamic range 80 db input resistance differential input 500 2,500 w input capacitance differential input 2 pf signal output limiter flatness C75 dbm to +5 dbm input signal at 10.7 mhz C1.5 +1.5 db with pin 9 to v pos via a 200 w resistor and pin 8 to v pos via a 200 w resistor output current at pins 8 or 9, proportional to v pos , ladj grounded 1.2 ma ladj open circuited 0.48 ma phase variation with input level C75 dbm to +5 dbm input signal at 10.7 mhz 3 log (rssi ) output nominal slope at 10.7 mhz; (0.0075 v pos )/db 37.5 mv/db at 45 mhz 35 mv/db slope accuracy untrimmed at 10.7 mhz C15 5 +15 % intercept sinusoidal input; independent of v pos C88.33 dbm logarithmic conformance C75 dbm to +5 dbm input signal at 10.7 mhz C1.5 0.4 +1.5 db nominal output input level = C75 dbm 0.5 v input level = C35 dbm 2 v input level = +5 dbm 3.5 v accuracy over temperature after calibration at C35 dbm at 10.7 mhz C3 3 db t min to t max video response time from onset of input signal until output reaches 400 ns 95% of final value power-down interface power-up response time time delay following hi transition until 3.5 m s device meets full specifications ac coupled with 100 pf coupling capacitors input bias current logical hi input (see figure 12) 1 na logical lo input 4 m a power supply operating range 4.5 5.5 v powered-up current zero signal input 13 ma t min to t max 13 20 ma powered-down current t min to t max 65 200 m a specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. specifications subject to change without notice.
AD606 rev. 0 C3C ordering guide temperature model range package option AD606jn 0 c to +70 c 16-pin plastic dip (n-16) AD606jr 0 c to +70 c 16-pin narrow-body soic ( r-16a) pin description plastic dip (n) and small outline (r) packages inlo comm ilog bfin isum vlog opcm lmlo lmhi ladj fil2 fil1 vpos prup comm inhi 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view (not to scale) AD606 absolute maximum ratings 1 supply voltage v pos . . . . . . . . . . . . . . . . . . . . . . . . . . . . +9 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . 600 mw operating temperature range . . . . . . . . . . . . . 0 c to +70 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 16-pin plastic dip package: q ja = 85 c/watt 16-pin soic package: q ja = 100 c/watt warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD606 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin functions pin mnemonic function 1 inlo differential rf input C75 dbm to +5 dbm, inverting, ac coupled. 2 comm power supply common connect to ground. 3 isum log detector summing node 4 ilog log current output normally no connection; 2 m a/db output current. 5 bfin buffer input optionally used to realize low frequency post-demodulation filters. 6 vlog buffered log output 37.5 mv/db (100 mv to 4.5 v). 7 opcm output common connect to ground. 8 lmlo differential limiter output 1.2 ma full-scale output current. open collector output must be pulled up to vpos with r 400 w . 9 lmhi differential limiter output 1.2 ma full-scale output current. open collector output must be pulled up to vpos with r 400 w . 10 ladj limiter level adjustment optionally used to adjust limiter output current. 11 fil1 offset loop low-pass filter normally no connection; a capacitor be tween fil1 and fil2 may be added to lower the filter cutoff frequency. 12 fil2 offset loop low-pass filter normally no connection; see above. 13 vpos positive supply connect to +5 v at 13 ma. 14 prup power up cmos (5 v) logical high = device on ( ? 65 mw). cmos (0 v) logical low = device off ( ? 325 m w). 15 comm power supply common connect to ground. 16 inhi differential rf input C75 dbm to +5 dbm, noninverting, ac coupled.
AD606 rev. 0 C4C input level conventions rf logarithmic amplifiers usually have their input specified in dbm, meaning decibels with respect to 1 mw. unfortu- nately, this is not precise for several reasons. 1. log amps respond not to power but to voltage. in this re- spect, it would be less ambiguous to use dbv (decibels referred to 1 v) as the input metric. also, power is dependent on the rms (root mean-square) value of the signal, while log amps are not inherently rms responding. 2. the response of a demodulating log amp depends on the waveform. convention assumes that the input is sinusoidal. however, the AD606 is capable of accurately handling any input waveform, including ac voltages, pulses and square waves, gaussian noise, and so on. see the ad640 data sheet, which covers the effect of waveform on logarithmic intercept, for more information. 3. the impedance in which the specified power is measured is not always stated. in the log amp context it is invariably as- sumed to be 50 w . thus, 0 dbm means 1 mw rms in 50 w , and c orresponds to an rms voltage of (1 mw 50 w ), or 224 mv. popular convention requires the use of dbm to simplify the comparison of log amp specifications. unless otherwise stated, sinusoidal inputs expressed as dbm in 50 w are used to specify the performance of the AD606 throughout this data sheet. we will also show the corresponding rms voltages where it helps to clarify the specification. noise levels will likewise be given in dbm; the response to gaussian noise is 0.5 db higher than for a sinusoidal input of the same rms value. note that dynamic range, being a simple ratio, is always speci- fied simply as db, and the slope of the logarithmic transfer function is correctly specified as mv/db, not as mv/dbm. logarithmic slope and intercept a generalized logarithmic amplifier having an input voltage v in and output voltage v log must satisfy a transfer function of the form v log = v y log 10 (v in /v x ) where, in the case of the AD606, the voltage v in is the differ- ence between the voltages on pins inhi and inlo, and the voltage v log is that measured at the output pin vlog. v y and v x are fixed voltages that determine the slope and intercept of the logarithmic amplifier, respectively. these parameters are inherent in the design of a particular logarithmic amplifier, although may be adjustable, as in the AD606. when v in = v x , the logarithmic argument is one, hence the logarithm is zero. v x is, therefore, called the logarithmic intercept voltage because the output voltage v log crosses zero for this input. the slope volt- age v y is can also be interpreted as the volts per decade when using base-10 logarithms as shown here. note carefully that v log and vlog in the above paragraph (and elsewhere in this data sheet) are different. the first is a voltage; the second is a pin designation. this equation suggests that the input v in is a dc quantity, and, if v x is positive, that v in must likewise be positive, since the logarithm of a negative number has no simple meaning. in fact, in the ad 606, the response is independent of the sign of v in because of the particular way in which the circuit is built. this is part of the demodulating nature of the amplifier, which results in an alternating input voltage being transformed into a quasi-dc (rectified and filtered) output voltage. the single supply nature of the AD606 results in common-mode level of the inputs inhi and inlo being at about +2.5 v (us- ing the recommended +5 v supply). in normal ac operation, this bias level is developed internally and the input signal is coupled in through dc blocking capacitors. any residual dc off- set voltage in the first stage limits the logarithmic accuracy for small inputs. in ac operation, this offset is automatically and continuously nulled via a feedback path from the last stage, pro- vided that the pins inhi and inlo are not shorted together, as would be the case if transformer coupling were used for the signal. while any logarithmic amplifier must eventually conform to the basic equation shown above, which, with appropriate elabora- tion, can also fully account for the effect of the signal waveform on the effective intercept, 1 it is more convenient in rf applica- tions to use a simpler expression. this simplification results from first, assuming that the input is always sinusoidal, and sec- ond, using a decibel representation for the input level. the stan- dard representation of rf levels is (incorrectly, in a log amp context) in terms of power, specifically, decibels above 1 milli- watt (dbm) with a presumed impedance level of 50 w . that be- ing the case, we can rewrite the transfer function as v log = v y (p in p x ) where it must be understood that p in means the sinusoidal input power level in a 50 w system, expressed in dbm, and p x is the intercept, also expressed in dbm. in this case, p in and p x are simple, dimensionless numbers. (p x is sometimes called the logarithmic offset, for reasons which are obvious from the above equation.) v y is still defined as the logarithmic slope, usu- ally specified as so many millivolts per decibel, or mv/db. in the case of the AD606, the slope voltage, v y , is nominally 750 mv when operating at v pos = 5 v. this can also be ex- pressed as 37.5 mv/db or 750 mv/decade; thus, the 80 db range equates to 3 v. figure 1 shows the transfer function of the AD606. the slope is closely proportional to v pos , and can more generally be stated as v y = 0.15 v pos. thus, in those applica- tions where the scaling must be independent of supply voltage, this must be stabilized to the required accuracy. in applications where the output is applied to an a/d converter, the reference vlog ?volts dc input signal ?dbm 4 0 +20 1 0.5 ?0 ?00 2 1.5 2.5 3 3.5 0 ?0 ?0 ?0 slope = 37.5mv/db intercept at ?8.33dbm figure 1. nominal transfer function 1 see, for example, the ad640 data sheet, which is published in section 3 of the special linear reference manual or section 9.3 of the 1992 amplifier applications guide.
AD606 rev. 0 C5C in applications where v log is taken to an a/d converter which allows the use of an external reference, this reference input should also be connected to the same +5 v supply. the power supply voltage may be in the range +4.5 v to +5.5 v, providing a range of slopes from nominally 33.75 mv/db (675 mv/ de- cade) to 41.25 mv/db (825 mv/decade). a buffer amplifier, having a gain of two, provides a final output scaling at v log of 37.5 mv/db (750 mv/decade). this low- impedance output can run from close to ground to over +4 v (using the recommended +5 v supply) and is tolerant of resis- tive and capacitive loads. further filtering is provided by a con- jugate pole pair, formed by internal capacitors which are an integral part of the output buffer. the corner frequency of the overall filter is 2 mhz, and the 10%C90% rise time is 150 ns. later, we will show how the slope and intercept can be altered using simple external adjustments. the direct buffer input bfin is used in these cases. the last limiter output is available as complementary currents from open collectors at pins lmhi and lmlo. these currents are each 1.2 ma typical with ladj grounded and may be con- verted to voltages using external load resistors connected to vpos; typically, a 200 w resistor is used on just one output. the voltage gain is then over 90 db, resulting in a hard-limited output for all input levels down to the noise floor. the phasing is such that the voltage at lmhi goes high when the input (inhi to inlo) is positive. the overall delay time from the sig- nal inputs to the limiter outputs is 8 ns. of particular impor- tance is the phase stability of these outputs versus input level. at 50 mhz, the phase typically remains within 4 from C70 dbm to +5 dbm. the rise time of this output (essentially a square wave) is about 1.2 ns, resulting in clean operation to more than 70 mhz. offset-control loop the offset-control loop nulls the input offset voltage, and sets up the bias voltages at the input pins inhi and inlo. a full understanding of this offset-control loop is useful, particularly when using larger input coupling capacitors and an external fil- ter capacitor to lower the minimum acceptable operating fre- quency. the loops primary purpose is to extend the lower end for that converter should be a fractional part of v pos , if possible. the slope is essentially independent of temperature. the intercept p x is essentially independent of either the supply voltage or temperature. however, the AD606 is not factory cali- brated, and both the slope and intercept may need to be exter- nally adjusted. following calibration, the conformance to an ideal logarithmic law will be found to be very close, particularly at moderate frequencies (see figure 14), and still acceptable at the upper end of the frequency range (figure 15). circuit description figure 2 is a block diagram of the AD606, which is a complete logarithmic amplifier system in monolithic form. it uses a total of nine limiting amplifiers in a successive detection scheme to closely approximate a logarithmic response over a total dynamic range of 90 db (figure 2). the signal input is differential, at nodes inhi and inlo, and will usually be sinusoidal and ac coupled. the source may be either differential or single-sided; the input i mpedance is about 2.5 k w in parallel with 2 pf. seven of the amplifier/detector st ages handle inputs from C80 dbm (32 m v rms) up to about C14 dbm (45 mv rms). the noise floor is about C83 dbm (18 m v rms). another two stages receive the input attenuated by 22.3 db, and respond to inputs up to +10 dbm (707 mv rms). the gain of each of these stages is 11.15 db and is accurately stabilized over temperature by a precise biasing system. the detectors provide full-wave rectification of the alternating signal present at each limiter output. their outputs are in the form of currents, proportional to the supply voltage. each cell incorporates a low-pass filter pole, as the first step in recovering the average value of the demodulated signal, which contains ap- preciable energy at even harmonics of the input frequency. a further real pole can be introduced by adding a capacitor be- tween the summing node isum and vpos. the summed de- tector output currents are applied to a 6:1 reduction current mirror. its output at ilog is scaled 2 m a/db, and is converted to voltage by an internal load resistor of 9.375 k w between ilog and opcm (output common, which is usually grou nded). the nominal slope at this point is 18.75 mv/db (375 mv/ decade). lmlo opcm vlog bfin ilog comm inlo isum 3 2 1 4 5 6 8 7 14 15 16 13 12 11 9 10 ladj fil1 fil2 vpos prup comm lmhi inhi x2 reference and power up offset-null low-pass filter AD606 high-end detectors final limiter 9.375k w 9.375k w 12 m a/db main signal path 11.15 db/stage 2 m a/db 1.5k w 30k w 250 w 30k w x1 360k w 1.5k w 30pf 30pf two-pole sallen-key filter 2pf 360k w one-pole filter 2pf figure 2. AD606 simplified block diagram
AD606 rev. 0 C6C of the dynamic range in the case where the offset voltage of the first stage should be high enough to cause later stages to prema- turely enter limiting, because of the high dc gain (about 8000) of the main amplifier system. for example, an offset voltage of only 20 m v would become 160 mv at the output of the last stage in the main amplifier (before the final limiter section), driving the last stage well into limiting. in the absence of noise, this lim- iting would simply result in the logarithmic output ceasing to become any lower below a certain signal level at the input. the offset would also degrade the logarithmic conformance in this region. in practice, the finite noise of the first stage also plays a role in this regard, even if the dc offset were zero. figure 3 shows a representation of this loop, reduced to essen- tials. the figure closely corresponds to the internal circuitry, and correctly shows the input resistance. thus, the forward gain of the main amplifier section is 7 11.15 db, but the loop gain is lowered because of the attenuation in the network formed by +1 cf1 30pf cf2 30pf to final limiter stage rf2 360k w rf1 360k w rb1 30k w ra 2.5k w rb2 30k w c c2 c c1 0v c z r z fil1 fil2 +1 78db figure 3. offset control loop rb1 and rb2 and the input resistance ra. the connection po- larity is such as to result in negative feedback, which reduces the input offset voltage by the dc loop gain, here about 50 db, that is, by a factor of about 316. we use a differential representation, because later we will examine the consequences to the power-up response time in the event that the ac coupling capacitors c c1 and c c2 do not exactly match. note that these capacitors, as well as forming a high-pass filter to the signal in the forward path, also introduce a pole in the feedback path. internal resistors rf1 and rf2 in conjunction with grounded capacitors cf1 and cf2 form a low-pass filter at 15 khz. this frequency can optionally be lowered by the addition of an exter- nal capacitor c z , and in some cases a series resistor r z . this, in conjunction with the low-pass section formed at the input cou- pling, results in a two-pole high-pass response, falling of at 40 db/decade below the corner frequency. the damping factor of this filter depends on the ratio c z /c c (when c z >>c f ) and also on the value of r z . the inclusion of this control loop has no effect on the high frequency response of the AD606. nor does it have any effect on the low fre- quency response when the input amplitude is substantially above the input offset voltage . the loops effect is felt only at the lower end of the dynamic range, that is, from about 80 dbm to C70 dbm, and when the signal frequency is near the lower edge of the passband. thus, the small signal results which are obtained using the suggested model are not indicative of the ac response at moderate to high signal levels. figure 4 shows the response of this model for the default case (using c c = 100 pf and c z = 0) and with c z = 150 pf. in general, a maximally flat ac response occurs when c z is roughly twice c c (making due allowance for the internal 30 pf capacitors). thus, for audio applications, one can use c c = 2.7 m f and c z = 4.7 m f to achieve a high-pass corner (C3 db) at 25 hz. 90 70 ?0 100k 100m 10m 1m 10k 80 60 40 50 20 30 10 ?0 0 c z = 0pf c z = 150pf input frequency ?hz relative output ?db figure 4. frequency response of offset control loop for c z = 0 pf and c z = 150 pf (c c = 100 pf) however, the maximally flat ac response is not optimal in two special cases. first, where the rf input level is rapidly pulsed, the fast edges will cause the loop filter to ring. second, ringing can also occur when using the power-up feature, and the ac cou- pling capacitors do not exactly match in value. we will examine the latter case in a moment. ringing in a linear amplifier is an- noying, but in a log amp, with its much enhanced sensitivity to near zero signals, it can be very disruptive. to optimize the low level accuracy, that is, achieve a highly damped pulse response in this filter, it is recommended to in- clude a resistor r z in series with an increased value of c z . some experimentation may be necessary, but for operation in the range 3 mhz to 70 mhz, values of c c = 100 pf, c z = 1 nf and r z = 2 k w are near optimal. for operation down to 100 khz use c c = 10 nf, c z = 0.1 m f and r z = 13 k w . figure 5 shows typical connections for the AD606 with these filter components added. 7 8 1 2 3 4 5 6 9 10 15 16 14 13 AD606jn inlo vlog ilog isum comm bfin opcm lmlo lmhi fil2 fil1 vpos prup comm inhi ladj 12 11 c z r z figure 5. use of c z and r z for offset control loop compensation
AD606 rev. 0 C7C for operation above 10 mhz, it is not necessary to add the external capacitors cf1, cf2, and c z , although an improve- ment in low frequency noise can be achieved by so doing (see applications). note that the offset control loop does not materially affect the low-frequency cutoff at high input levels, when the offset voltage is swamped by the signal. power-up interface the AD606 features a power-saving mode, controlled by the logic level at pin 14 (prup). when powered down, the quies- cent current is typically 65 m a, or about 325 m w. a cmos logi- cal high applied to prup activates both internal references, and the system becomes fully functional within about 3.5 m s. when this input is a cmos logical low, the system shuts down to the quiescent level within about 5 m s. the power-up time is somewhat dependent on the signal level and can be degraded by mismatch of the input coupling capaci- tors. the explanation is as follows. when the AD606 makes the transition from powered-down to fully active, the dc bias voltage at the input nodes inhi and inlo (about +2.5 v) inevitably changes slightly, as base current in the input transistors flows in the bias resistors. in fact, first-order correction for this is in- cluded in the specially designed offset buffer amplifier, but even a few millivolts of change at these inputs represents a significant equivalent dbm level. now, if the coupling capacitors do not match exactly, some fractional part of this residual voltage step becomes coupled into the amplifier. for example, if there is a 10% capacitor mis- match, and inhi and inlo jump 20 mv at power-up, there is a 2 mv pulse input to the system, which may cause the offset control loop to ring. note that 2 mv is roughly 40 times greater than the amplitude of a sinusoidal input at C75 dbm. as long as the ringing persists, the AD606 will be blind to the actual in- put, and v log will show major disturbances. the solution to this problem is first, to ensure that the loop fil- ter does not ring, and second, to use well-matched capacitors at the signal input. use the component values suggested above to minimize ringing. applications note that the AD606 has more than 70 mhz of input band- width and 90 db of gain! careful shielding is needed to realize its full dynamic range, since nearly all application sites will be pervaded by many kinds of interference, radio and tv stations, etc., all of which the AD606 faithfully hears. in bench evalua- tion, we recommend placing all of the components in a shielded box and using feedthrough decoupling networks for the supply voltage. in many applications, the AD606s low power drain al- lows the use of a 6 v battery inside the box. basic rssi application figure 6 shows the basic rssi (receiver signal strength indica- tor) application circuit, including the calibration adjustments, either or both of which may be omitted in noncritical applica- tions. this circuit may be used as is in such measurement ap- plications as the log/if strip in a spectrum or network analyzer or, with the addition of an fm or qpsk demodulator fed by the limiter outputs, as an if strip in such communications applica- tions as a gsm digital mobile radio or fm receiver. the slope adjustment works in this way: the buffer amplifier (which forms part of a sallen-key two-pole filter, see figure 2) has a dc gain of plus two, and the resistance from bfin (buffer in) to opcm (output common) is nominally 9.375 k w . this resistance is driven from the logarithmic detector sections with a current scaled 2 m a/db, generating 18.75 mv/db at bfin, hence 37.5 mv/db at v log now, a resistor (r4 in figure 6) connected directly between bfin and vlog would form a controlled positive-feedback network with the internal 9.375 k w resistor which would raise the gain, and thus increase the slope voltage, while the same external resistor connected between bfin and ground would form a shunt across the internal resis- tor and reduce the slope voltage. by connecting r4 to a potenti- ometer r2 across the output, the slope may be adjusted either way; the value for r4 shown in figure 6 provides approximately 10% range, with essentially no effect on the slope at the midposition. the intercept may be adjusted by adding a small current into bfin via r1 and r3. the AD606 is designed to have the nomi- nal intercept value of C88 dbm when r1 is centered using this network, which provides a range of 5 db. r4 174k w r3 412k w +5v r2 50k w slope adjustment 10% rf input 100pf 100pf 0.1 m f r5 200 w r1 200k w intercept adjustment 5db limiter output logarithmic output +5v 7 8 1 2 3 4 5 6 9 10 15 16 14 13 inlo vlog ilog isum comm bfin opcm lmlo lmhi fil2 fil1 vpos prup comm inhi ladj 12 11 AD606 51.1 w nc nc figure 6. basic application circuit showing optional slope and intercept adjustments
AD606 rev. 0 C8C adjustment procedure the slope and intercept adjustments interact; this can be mini- mized by reducing the resistance of r1 and r2, chosen here to minimize power drain. calibration can be achieved in several ways: the simplest is to apply an rf input at the desired oper- ating frequency which is amplitude modulated at a relatively low frequency (say 1 khz to 10 khz) to a known modulation in- dex. thus, one might choose a ratio of 2 between the maximum and minimum levels of the rf amplitude, corresponding to a 6 db (strictly, 6.02 db) change in input level. the average rf level should be set to about C35 dbm (the midpoint of the AD606s range). r2 is then adjusted so that the 6 db input change results in the desired output voltage change, for ex- ample, 226 mv at 37.5 mv/db. a better choice would be a 4:1 ratio (12.04 db), to spread the residual error out over a larger segment of the whole transfer function. if a pulsed rf generator is available, the decibel incre- ment might be enlarged to 20 db or more. using just a fixed- level rf generator, the procedure is more time consuming, but is carried out in just the same way: manually change the level by a known number of decibels and adjust r2 until v log varies by the corresponding voltage. having adjusted the slope, the intercept may now be simply ad- justed using a known input level. a value of C35 dbm (397.6 mv rms, or 400 mv to within 0.05 db) is recommended, and if the standard scaling is used (p x = C88.33 dbm, v y = 37.5 mv/ db), then v log should be set to +2 v at this input level. a low cost audio through rf power meter figure 7 shows a simple power meter that uses the AD606 and an icl7136 3-1/2 digit dmm ic driving an lcd readout. the circuit operates from a single +5 v supply and provides direct readout in dbm, with a resolution of 0.1 dbm. in contrast to the limited dynamic range of the diode and thermistor-styled sensors used in power meters, the AD606 can measure signals from below C80 dbm to over +10 dbm. an op- tional 50 w termination is included in the figure; this could form the lower arm of an external attenuator to accommodate larger signal levels. by the simple expedient of using a 13 db attenua- tor, the lcd reading now becomes dbv (decibels above 1 v rms). this requires a series resistor of 174 w , presenting an input resistance of 224 w . alternatively, the input resistance can be raised to 600 w using 464 w and 133 w . it is important to note that the AD606 inputs must be ac coupled. to extend the low frequency range, use larger coupling capacitors and an external loop filter, as outlined earlier. the nominal 0.5 v to 3.5 v output of the AD606 (for a C75 dbm to +5 dbm input) must be scaled and level shifted to fit within the +1 v to +4.5 v common-mode range of the icl7136 for the +5 v supply used. this is achieved by the passive resistor network of r1, r2, and r3 in conjunction with the bias net- works of r4 through r7, which provide the icl7136 with its reference voltage, and r9 through r11, which set the intercept. the icl7136 measures the differential voltage between in hi and in lo, which ranges from C75 mv to +5 mv for a C75 dbm to +5 dbm input. to calibrate the power meter, first adjust r6 for 100 mv be- tween ref hi and ref lo. this sets the initial slope. then adjust r10 to set in lo 80 mv higher than in hi. this sets the initial intercept. the slope and intercept may now be adjusted using a calibrated signal generator as outlined in the previous section. to extend the low frequency limit of the system to audio fre- quencies, simply change c1, c2, and c3 to 4.7 m f. the limiter output of the AD606 may be used to drive the high- impedance input of a frequency counter. c4 1 m f r1 1m w dbm input c1 * 100pf c2 * 100pf 0.1 m f 200 w +5v 7 8 1 2 3 4 5 6 9 10 15 16 14 13 inlo vlog ilog isum comm bfin opcm lmlo lmhi fil2 fil1 vpos prup comm inhi ladj 12 11 AD606jn 51.1 w 174 dbv input c3 * 150pf optional drive to frequency counter +5v r9 5k w r8 100k w r10 100k w r2 54.9k w +5v r3 54.9k w icl7136cpl v 26 0.1 m f 33 34 180k w 50pf 40 39 38 1.8m w 0.1 m f 0.047 m f 27 28 29 ?5.0 display +5v 1 0.1 m f in hi in lo 30 31 common ref lo ref hi 36 35 32 r4 4.99k w +5v r5 4.32k w r6 500 w r7 162 w 100mv 2.513v nom 80mv for 0 dbm signal input 2.433v nom +5v nc nc nc * for audio measurements change c1, c2, and c3 to 4.7 m f; positive polarity connect to pins 1, 16 w ? figure 7. a low cost rf power meter
AD606 rev. 0 C9C low frequency applications with reasonably sized input coupling capacitors and an optional input low-pass filter, the AD606 can operate to frequencies as low as 200 hz with good log conformance. figure 8 shows the schematic, with the low-pass filter included in the dashed box. this circuit should be built inside a die cast box and the signal brought in through a coaxial connector. the circuit must also have a low-pass filter to reject the attenuated rf signals that would otherwise be rectified along with the desired signal and be added to the log output. the shielded and filtered circuit has a 90 db dynamic range, as shown in figure 9. in this circuit, r4 and r5 form a 20 db attenuator that extends the input range to 10 v rms. r3 isolates loads from vlog. ca- pacitors c1 and c2 (4.7 m f each), r1, r2, and the AD606s in- put resistance of 2.5 k w form a 100 hz high-pass filter that is before the AD606; the corner frequency of this filter must be well below the lowest frequency of interest. in addition, the offset-correction loop introduces another pole at low signal lev- els that is transformed into another high-pass filter because it is in a feedback path. this indicates that there has to be a gradual transition from a 40 db roll off at low signal levels to a 20 db roll off at high signal levels, at which point the feedback low pass filter is effectively disabled since the incoming signal swamps the feedback signal. this low-pass filter introduces some attenuation due to r1 and r2 in conjunction with the 2.5 k w input resistance of the AD606. to minimize this effect, the value of r1 and r2 should be kept as small as possibleC100 w is a good value since it bal- ances the need to reduce the attenuation as mentioned above with the requirement for r1 and r2 to be much larger then the impedance of c1 and c2 at the low-pass corner frequency, in our case about 1 mhz. 4 ?0 40 3 1 ?0 2 0 20 ?0 ?0 input signal ?dbm vlog ?volts dc 0 1khz ?10mhz 100hz 90db 3.5v figure 9. performance of low frequency circuit at 100 hz and 1 khz to 10 mhz (note attenuation) r3 1k w c4 4.7 m f to dvm 0.1 m f +5v 7 8 1 2 3 4 5 6 9 10 15 16 14 13 inlo vlog ilog isum comm bfin opcm lmlo lmhi fil2 fil1 vpos prup comm inhi ladj 12 11 AD606jn nc nc nc r5 51.1 w ac input c1 4.7 m f c2 4.7 m f r1 100 w r2 100 w c3 680pf r4 453 w low-pass filter diecast box 20db attenuator figure 8. circuit for low frequency measurements
rev. 0 C10C AD606Ctypical characteristics 5 ?5 20 ?0 ?0 ?0 ?5 ?0 0 ? 0 ?0 ?0 input level ?dbm normalized phase shift ?degrees 10.7mhz 45mhz 70mhz figure 11. normalized limiter phase response vs. input level at 10.7 mhz, 45 mhz, and 70 mhz 10 ? ? ?0 ? ?0 1 ? 0 2 3 4 0 ?0 ?0 input amplitude ?dbm logarithmic error ?db t a = ?5 t a = +25 t a = +70 figure 14. logarithmic conform- ance as a function of input level at 10.7 mhz at C25 c, +25 c, and +70 c figure 17. v log response to a 10.7 mhz cw signal modulated by a 25 m s wide pulse with a 25 khz repetition rate using 200 pf input coupling capacitors. the input sig- nal goes from +5 dbm to C75 dbm in 20 db steps. normalized limiter output ?db input level ?dbm 0.5 ?.5 10 ?.5 ?.5 ?0 ?.5 ?0 ?.5 ?.5 ?.5 0 ?0 ?0 ?0 ?0 ?0 ?0 10.7mhz 45mhz 70mhz figure 10. normalized limiter amplitude response vs. input level at 10.7 mhz, 45 mhz and 70 mhz 4.5 0 +10 1 .5 ?0 ?0 2 1.5 2.5 3 3.5 4 0 ?0 ?0 input power ?dbm v log ?volts dc t a = +25 c v s = 4.5v v s = 5.5v v s = 5v figure 13. v log plotted vs. input level at 10.7 mhz as a function of power supply voltage figure 16. limiter response at onset of 10.7 mhz modulated pulse at C75 dbm using 200 pf input coupling capacitors prup voltage ?volts power supply current ?ma 14 0 5 6 2 0.5 4 0 12 8 10 4.5 4 3.5 3 2.5 2 1.5 1 figure 12. supply current vs. prup voltage at +25 c t a = +25 c t a = +70 c 5 ? 10 ? ? ?0 ? ?0 1 ? 0 2 3 4 0 ?0 ?0 input amplitude ?dbm logarithmic error ?db t a = ?5 c figure 15. logarithmic conform- ance as a function of input level at 45 mhz at C25 c, +25 c, and +70 c figure 18. limiter response at onset of 70 mhz modulated pulse at C55 dbm using 200 pf input coupling capacitors
AD606 rev. 0 C11C figure 19. v log output for a pulsed 10.7 mhz input; top trace: C35 dbm to +5 dbm; middle trace: C15 dbm to C55 dbm; bottom trace: C35 dbm to C75 dbm figure 20. example of test signal used for figure 19 figure 21. v log output for 10.7 mhz cw input with prup tog- gled on and off; top trace: +5 dbm input; middle trace: C35 dbm input; bottom trace: C75 dbm; prup input from hp8112a:0 to 4 v, 10 m s pulse width with 10 khz repetition rate modulated pulse tests swept-gain tests c1 100pf c2 100pf 51.1 w c3 150pf +5v nc nc nc 7 8 1 2 3 4 5 6 9 10 15 16 14 13 inlo vlog ilog isum comm bfin opcm lmlo lmhi fil2 fil1 vpos prup comm inhi ladj 12 11 AD606jn rf input tektronix 7704a mainframe oscilloscope 7a18 amp p6201 probes 7b53a time-base 6137 probes 7a24 amp 10 x attn 0.1 m f +5v ad602 ?0db to +30db (10.7mhz swept gain tests only) fluke 6082a synthesized signal generator hewlett packard 8112a pulse generator 200 w 200 w figure 22. test setup for characterization data
AD606 rev. 0 C12C outline dimensions dimensions shown in inches and (mm). 16-pin plastic (n-16) package 0.125 (3.18) min 0.035 (0.89) 0.18 (4.57) 0.3 (7.62) 0.87 (22.1) max 0.25 (6.35) 0.31 (7.87) 0.18(4.57) max 0.011 (0.28) 18 9 16 0.018 (0.46) 0.033 (0.84) 0.1 (2.54) 16-pin plastic narrow-body small outline ic (r-16a) package printed in u.s.a. c1698C24C7/92

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